This invention relates generally to the manufacture of circuit devices on semiconductor wafers and more specifically to a method for testing an etch process for its likelihood of producing a manufacturing defect called a blind hole that can occur in a contact layer of a wafer.
The circuit device chips of a semiconductor wafer are commonly formed as a multilayer structure. Some layers, called contact layers, form electrical interconnections between circuit nodes in the structures above and below the contact layer. A wafer can have several contact layers, and the layer below the contact layer can be the substrate or one of the layers that are formed over the substrate.
The contact layer is formed initially as a layer of dielectric material. The dielectric is commonly silicon dioxide (called oxide). An interconnection is in the form of a cylinder of metal or other conductive material that extends through the dielectric from the layer above to the layer or substrate below. The dielectric supports the conductors, and it initially acts as a template for forming the interconnections. Commonly, the interconnections are formed by first creating cylindrical holes at selected positions in the contact layer.
When the contact layer is located over the substrate, a hole in the dielectric layer extends into the substrate for a distance that is suitable for making electrical contact to circuit nodes at this location in the substrate. The hole through the dielectric of the contact layer and the substrate hole are then filled with any suitable conductor, commonly tungsten.
The holes in the contact layer can be formed in any suitable way, but this invention is particularly intended for use with a high density plasma etch. Because the holes are long in relation to their diameter, etching can sometimes form only a partial hole: a hole that does not extend completely through the dielectric of the contact layer. The resulting partial hole is called a blind hole. When a conductor is formed in a blind hole; it does not make electrical contact with the circuit node in the substrate below the contact layer.
Wafers commonly have several contact layers and the problem of blind holes can occur in any layer.
The holes can be detected at the surface of the contact layer but blind holes can not be distinguished from normal holes in this way.
Blind hole defects can be detected by sectioning the wafer through one or more holes and then viewing the section with a scanning electron microscope. A normal hole and a blind hole can be clearly distinguished in this test, but the test is time consuming and only a few holes can be tested.
One object of our invention is to provide a new and improved method for detecting blind holes. A more specific object is to provide a new and improved method for processing a test wafer to determine how the associated etch process affects the number of blind holes in the contact layer.
After the holes are etched in the dielectric of the contact layer in a first etch step and in the underlying layer in a second etch step, we strip the contact layer to expose the underlying surface. It is an advantage of our test method that these two etch steps are used in the same way in wafer manufacture.
A wafer has a repeating pattern of identical units which are called chips. The number of holes in a contact layer depends on the chip design, but a chip may have more than ten thousand holes. A problem occurring on contact etchers or in the etching process can induce a blind contact, and the blind contact might occur randomly on any contact hole. The location of these blind holes can not be predicted beforehand.
Therefore, we use a known optical apparatus to provide a view of the wafer, and we compare the contact pattern between each chip to find out if any blind hole has occurred. The data from this comparison is a useful indicator of the effectiveness of the process for etching the contact layer.
Other objects and features of our invention will appear in the description of the preferred embodiment of the invention.